FUJITSU LQFP-52P - Manual (Page 12)

9
■ MCU board I/F connector (CN1, CN2, and CN3)
CN1 and CN2 are MCU board I/F connectors. CN3 is the incorrect insertion prevention socket of a
MCU board. The pin assignment of the MCU board I/F connector CN1 is shown in Table 5, and the
pin assignment of the MCU board I/F connector CN2 is shown in Table 6.
Table 5 Pin Assignment of the MCU Board I/F Connector CN1
Connector
Pin
Number
Evaluation
MCU Pin
Number
Signal
name
Connector
Pin
Number
Evaluation
MCU Pin
Number
Signal
name
Connector
Pin
Number
Evaluation
MCU Pin
Number
Signal
name
1 A9 PC4 41 E2 LVR3 81 P3 BSOUT
2 B9 PC1 42 E1 LVSS 82 P4 BDBMX
3 C9 PC2 43 F4 LVDREXT 83 R1 P83
4 D9 PC3 44 F3 LVDBGR 84 R2 BRSTX
5 A8 PC0 45 F2 LVDENX 85 R3 X0A
6 B8 PB4 46 F1 P22A 86 R4 RSTX
7 C8 PB5 47 - GND 87 T1 ROMS1
8 D8 PB6 48 - GND 88 T2 BSIN
9 A7 PB7 49 G4 P20A 89 T3 Vss
10 B7 PB2 50 G3 NC1 90 T4 X0
11 C7 PB0 51 G2 P21A 91 U1 BEXCK
12 D7 PB1 52 G1 P23A 92 U2 X1
13 A6 PB3 53 H4 P24A 93 U3 MOD
14 B6 PA2 54 H3 P25A 94 U4 PF2
15 C6 P95 55 H2 P26A 95 V1 X1A
16 D6 PA0 56 H1 P27A 96 V2 Vcc53
17 A5 PA3 57 J4 P24B 97 - GND
18 B5 P94 58 J3 P50 98 - GND
19 C5 P90 59 J2 P23B 99 V3 PINT0
20 D5 P91 60 J1 P51 100 V4 PSEL_EXT
21 A4 PA1 61 K1 P52 101 R5 PF1
22 A3 P93 62 K2 P55 102 T5 PF0
23 - GND 63 K3 P54 103 U5 NC2
24 - GND 64 K4 P53 104 V5 PENABLE
25 A2 CSVENX 65 L1 P70 105 R6 APBENX
26 A1 Vss 66 L2 P74 106 T6 PINT1
27 B4 P92 67 L3 P73 107 U6 PCLK
28 B3 TCLK 68 L4 P72 108 V6 PADDR0
29 B2 LVCC 69 M1 P71 109 R7 PACTIVE
30 B1 LVDIN 70 M2 P76 110 T7 PLOCK
31 C4 Cpin 71 M3 P80 111 U7 PWRITE
32 C3 Vcc51 72 M4 P77 112 V7 PADDR1
33 C2 LVDENX2 73 - GND 113 R8 PADDR2
34 C1 LVR4 74 - GND 114 T8 PADDR3
35 D4 TESTO 75 N1 P75 115 U8 PADDR4
36 D3 LVDOUT 76 N2 P82 116 V8 PADDR5
37 D2 LVR2 77 N3 PG0 117 R9 PADDR7
38 D1 BGOENX 78 N4 P84 118 T9 PRDATA0
39 E4 LVR1 79 P1 P81 119 U9 PADDR6
40 E3 LVR0 80 P2 ROMS0 120 V9 PRDATA1