Mitel DISTRIBUTED HYPERCHANNEL MT90840 - Manual (Page 19)

Preliminary Information
MT90840
2-249
Figure 12a - 2.048 Mbps Add/Drop Mode TPDM
Addressing
Figure 12b - 2.048 Mbps Add/Drop Mode RPCM
Addressing
4.096 Mbps Mode
The 4.096 Mbps mode has 8 input and 8 output
streams, and 64 channels per stream. Therefore 3
bits are used to address the 8 streams, and 6 bits
are used to address the 64 channels. Figure 13a
shows how the Transmit Path Data Memory is read in
this mode. Each of the 512 input channels is mapped
to an address in the TPDM. CPU reads require the 2
LSBs of the CAR Register, and the 7 LSBs of the
address bus. The source-channel address-value
written in the TPCM requires 9 bits.
Figure 13b shows how the Receive Path Connection
Memory is addressed by the CPU in 4.096 Mbps
mode. Each of the 512 output channels has a
control-address in the RPCM. CPU accesses require
the 2 LSBs of the CAR Register, and the 7 LSBs of
the address bus. Per-channel direction control in this
mode is the same as the 2.048 Mbps Balanced
mode.
Figure 13a - 4.096 Mbps TPDM Addressing
Figure 13b - 4.096 Mbps RPCM Addressing
8.192 Mbps Mode
The 8.192 Mbps mode has 4 input and 4 output
streams, and 128 channels per stream. Therefore 2
bits are used to address the 4 streams, and 7 bits
are used to address the 128 channels. Figure 14a
shows how the Transmit Path Data Memory is read in
this mode. Each of the 512 input channels is mapped
to an address in the TPDM. CPU reads require the 2
LSBs of the CAR Register, and the 7 LSBs of the
address bus. The source-channel address-value
written in the TPCM requires 9 bits.
Figure 14b shows how the Receive Path Connection
Memory is addressed by the CPU in 8.192 Mbps
mode. Each of the 512 output channels has a
control-address in the RPCM. CPU accesses require
the 2 LSBs of the CAR Register, and the 7 LSBs of
the address bus. Per-channel direction control in this
mode is the same as the 2.048 Mbps Balanced
mode.
.
.
STi0, Ch0
STi0, Ch1
STi7, Ch30
STi7, Ch31
STo0 (STi8), Ch0
000H
001H
0FEH
0FFH
100H
101H
1FEH
1FFH
.
.
CPU Port Addressing:
TPCM Contents:
8 7 6 5 4 3 2 1 0
1 0 6 5 4 3 2 1 0
Stream
Stream
Channel
Channel
Address Bus CAR
Bits 8:5 select one of 16 streams.
Bits 4:0 select one of 32 channels
per stream.
TPDM
Address
STo0 (STi8), Ch1
STo7 (STi15), Ch30
STo7 (STi15), Ch31
Serial I/O
Channel
.
.
STo0, Ch0
STo0, Ch1
STo7, Ch30
STi7, Ch31
STi0 (STo8), Ch0
000H
001H
0FEH
0FFH
100H
101H
1FEH
1FFH
.
.
RPCM
Address
STi0 (STo8), Ch1
STi7 (STo15), Ch30
STi7 (STo15), Ch31
Serial Output
Channel
CPU Port Addressing:
1 0 6 5 4 3 2 1 0
Stream Channel
Address Bus CAR
.
.
STi0, Ch0
STi0, Ch1
000H
001H
CPU Port Addressing:
TPCM Contents:
8 7 6 4 3 2 1 0
1 0 6 4 3 2 1 0
Stream
Stream
Channel
Channel
Address Bus CAR
Bits 8:6 select one of 8 streams.
Bits 5:0 select one of 64 channels
per stream.
STi7, Ch62
STi7, Ch63
1FEH
1FFH
5
5
Serial Input
Channel TPDM
Address
.
.
STo0, Ch0
STo0, Ch1
000H
001H
STo7, Ch62
STo7, Ch63
1FEH
1FFH
RPCM
Address Serial Output
Channel
CPU Port Addressing:
1 0 6 4 3 2 1 0
Stream Channel
Address Bus CAR
5