Mitel DISTRIBUTED HYPERCHANNEL MT90840 - Manual (Page 5)

Preliminary Information
MT90840
2-235
59 10 TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller, placing it
in the
Test-Logic-Reset state. This pin is pulled high internally when not driven.
This pin should be pulsed low on power-up, or held low continuously, to ensure
that the MT90840 is in the normal functional state, and not the test state.
60 11 TCK Test Clock (Input). Provides the clock to the JTAG test logic. This pin is pulled high
by an internal pull-up when not driven.
61 12 TMS Test Mode Select (Input). JTAG signal that controls the state transitions of the
TAP controller, sampled on rising TCK. This pin is pulled high by an internal
pull-up when not driven.
62 13 TDO Test Data (Output). JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in a high impedance state when JTAG scan is not enabled.
65 16 SPCKo Serial Port Clock (Output) In TM2 and TM3, this is a 4.096 MHz clock output
derived from the system 4.096 MHz reference. (As controlled by the C4/8R bit and
the INTCLK bit in the TIM Register.) This output is used to shift data in and out of
the serial port.
In TM1 and TM4, this output is automatically placed in high impedance.
For applications with the serial port running at 8.192 Mbps this output is not used,
and an 8.192 MHz clock source must be supplied at C4/8R1 or C4/8R2.
66-73 17-24 STo7-STo0 Serial Output Streams 7 to 0 (Bidirectional). Serial TDM data-streams at 2.048,
4.096 or 8.192 Mbps, with 32, 64 or 128 channels respectively per stream. For
2.048 and 4.096 Mbps applications, streams STo0-STo7 can be used, while for
8.192 Mbps, only streams STo0-STo3 are used (512 channel limit). These eight
bidirectional lines can be programmed as inputs or outputs (default) on a
per-channel basis.
76-83 32-39 AD0-AD7 Multiplexed Address/Data Bus (Bidirectional). These I/O lines provide an 8-bit
interface to a microprocessor for control and monitoring of the MT90840. These
pins function as eight input address lines to the Address Latch circuit as well as
eight data I/O lines.
84 40 R/W \ WR Read/Write \ Write (Input). In Motorola multiplexed-bus mode this input is
R/W, which controls the direction of the data bus lines (AD0-AD7) during a
microprocessor access. In Intel/National multiplexed-bus mode this input is WR,
an active low signal which configures the data bus lines (AD0-AD7) as inputs
during a microprocessor write access.
1,11
24,32,
43,53,
64,74
15,25,
41,55,
68,74,
90,10
0
V
SS
Ground.
2, 12,
25,33
44,54,
63,75
5, 14,
26,42
56,69,
75,91
V
DD
+5 Volt Power Supply.
Pin Description (continued)
Pin #
Name Description
84 100