Mc message channel: the message channel contents a, Dc direction control: dc set high indicates this c, When fdc = low (2.048, 4.096 or 8.192 mbps) the 51 – Mitel DISTRIBUTED HYPERCHANNEL MT90840 User Manual

Page 30: When fdc = high (2.048 mbps), the 512 dc bits can, Oe output enable. per-channel tristate control for, Ab8-11 source channel address. these 4 bits are us, Ab0-7 source channel address. in switching mode (m, Preliminary information

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MT90840

Preliminary Information

2-260

MC

Message Channel: The message channel contents are provided by the CPU in bits AB0-7 in the Rx Path Connection
Memory Low. If MC is HIGH, the contents of the corresponding location of RPCM Low are output on this serial port
channel. If MC is LOW, the contents of the corresponding location in RPCM Low act as an address for the Rx Path
Data Memory and so determine the source of the connection (input channels from the PDi0-7 port).

DC

Direction Control: DC set HIGH indicates this channel is an output. DC set LOW indicates this channel is an input.
The operation of this bit is modified by the state of FDC in the IMS Register.

When FDC = LOW (2.048, 4.096 or 8.192 Mbps) the 512 DC bits (256 at 2.048) each define the direction of a pair of
pins for each channel. When DC is set LOW the associated channel on the STo pin becomes an input, and the
corresponding channel on the same-number STi pin is automatically used as the output for this time slot. When DC
is set HIGH, STo is the output, and STi is the input for this time slot (default).

When FDC = HIGH (2.048 Mbps), the 512 DC bits can be used to control the direction of each individual 64 kbps
time slot present on the 16 serial I/O lines on a non-symmetrical basis; i.e. all 512 channels can be configured as
outputs or inputs or any mixed combination. If DC is LOW, this serial port channel is defined as input. If DC is HIGH,
this channel is defined as output. Note that the CPU still has to set OE to enable the output buffers on each channel
defined as an output.

OE

Output Enable. Per-channel tristate control for each channel on the serial port side. If FDC is HIGH, the 512 OE bits
enable the output for each of the 512 ST channels, unless the channel is defined as an input by the DC bit. In 4.096
and 8.192 Mbps modes, the OE bit enables the output buffer either on a STo pin, or an STi pin, as defined by the
accompanying DC bit.

AB8-11

Source Channel Address. These 4 bits are used along with AB0-7 to select any of the 2430 parallel incoming
channels from the parallel port and determine the switch connection to the 512 possible destination channels on the
serial port.

Receive Path Connection Memory High (RPCM High) - This is a 7-bit x 512-position memory.

7

6

5

4

3

2

1

0

MC

DC

OE

AB11

AB9

-

AB10

AB8

(RX Path CM High)

Used only in TM1, 2, & 3.

AB0-7

Source Channel Address. In switching mode (MC=LOW), these 8 bits are used along with AB8-11 to select one of
the 2430 incoming channels from the parallel port. In message mode (MC=HIGH), these 8 bits are programmed by
the CPU with the message patterns desired on the corresponding serial output channel.

Receive Path Connection Memory Low (RPCM Low) - This is an 8-bit x 512-position memory.

7

6

5

4

3

2

1

0

AB6

AB5

AB4

AB3

AB1

AB7

AB2

AB0

(RX Path CM Low)

Used only in TM1, 2 &3.

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