Motorola MC9S12GC-Family - Manual (Page 27)

Device User Guide — 9S12C128DGV1/D V01.05
27
1.4 Block Diagram
Figure 1-1 MC9S12C-Family Block Diagram
MSCAN
TXCAN
RXCAN
16K, 32K, 64K, 96K, 128K Byte Flash
1K, 2K, 4K Byte RAM
SCI
VDDR
VDDA
VSSA
VRH
VRL
ATD
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5 PAD3
PAD4
PAD5
PAD6
PAD7
PAD0
PAD1
PAD2
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3
IOC4
IOC5 PT3
PT4
PT5
PT6
PT7
PT0
PT1
PT2
RXD
TXD
SCK
MISO
PS3
PS0
PS1
PS2
SS SPI
PTAD
PTT
DDRT
PTS
DDRS
Voltage Regulator
VDD1
VSS1
PWM
Signals shown in Bold are not available on the 52 or 48 Pin Package
DDRAD
VDDA
VSSA
Timer
Module
VDDX
VSSX
VRH
VRL
VSSR
RESET
EXTAL
XTAL
BKGD
R/W
MODB/IPIPE1
XIRQ
NOACC/XCLKS
System
Integration
Module
(SIM)
HCS12
Periodic Interrupt
COP Watchdog
Clock Monitor
Background
PLL
VSSPLL
XFC
VDDPLL
Multiplexed Address/Data Bus
Multiplexed
Wide Bus
IRQ
LSTRB/TAGLO
ECLK
MODA/IPIPE0
PA
4
PA
3
PA
2
PA
1
PA
0
PA
7
PA
6
PA
5
TEST/VPP
ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR15 ADDR14 ADDR13
D
A
T
A12
D
A
T
A11
D
A
T
A10
DA
T
A
9
D
ATA
8
D
A
T
A15
D
A
T
A14
D
A
T
A13
PB4 PB3 PB2 PB1 PB0 PB7 PB6 PB5
ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 ADDR7 ADDR6 ADDR5
D
ATA
4
DA
T
A
3
DA
T
A
2
DA
T
A
1
DA
T
A
0
DA
T
A
7
DA
T
A
6
DA
T
A
5
PE3
PE4
PE5
PE6
PE7
PE0
PE1
PE2
DDRA DDRB
PTA PTB
DDRE
PTE
Clock and
Reset
Generation
Module
Debug12 Module
VDD2
VSS2
Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
CPU
PM3
PM4
PM5
PM0
PM1
PM2
PTM
DDRM
PW2
PW0
PW1
PW3
PW4
PW5 PP3
PP4
PP5
PP6
PP7
PP0
PP1
PP2
PTP
DDRP
PJ6
PJ7
PTJ
DDRJ
VDD1,2
VSS1,2
VDDX
VSSX
Internal Logic 2.5V
VDDPLL
VSSPLL
PLL 2.5V
I/O Driver 5V
VDDA
VSSA
A/D Converter 5V
VDDR
VSSR
Voltage Regulator 5V & I/O
VRL is bonded internally to VSSA
for 52 and 48 Pin packages
MOSI
Module
MUX
Keypad Interrupt
Key Int
MODC
MSCAN is not available on the
9S12GC Family Members