Motorola MC9S12GC-Family - Manual (Page 80)

Device User Guide — 9S12C128DGV1/D V01.05
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The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the
VREG Block User Guide for voltage level specifications.
9.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7 ).
Section 10 Oscillator (OSC) Block Description
Consult the OSC Block User Guide for information about the Oscillator module.
Section 11 Timer (TIM) Block Description
Consult the TIM_16B8C Block User Guide for information about the Timer module.
Section 12 Analog to Digital Converter (ATD) Block
Description
12.1 Device-specific information
12.1.1 VRL (voltage reference low)
In the 48 and 52 pin package versions, the VRL pad is bonded internally to the VSSA pin.
Consult the ATD_10B8C Block User Guide for further information about the A/D Converter module.
Section 13 Serial Communications Interface (SCI) Block
Description
Consult the SCI Block User Guide for information about the Asynchronous Serial Communications
Interface module.
Section 14 Serial Peripheral Interface (SPI) Block
Description
Consult the SPI Block User Guide for information about the Serial Peripheral Interface module.