M-Systems Flash Disk Pioneers Flash Memory - Manual (Page 10)

Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory
91-SR-014-02-8L 10
Enhanced EDC and ECC
The Error Detection Code (EDC) and Error Correction Code (ECC) developed for x2 technology is
based on M-Systems’ highly effective combination used in previous generation DiskOnChip
products. This system contains hardware-embedded EDC mechanism to detect errors on-the-fly and
software-embedded ECC mechanism to reduce silicon size and cost. The combination of hardware
and software results in the industry’s most cost-effective data reliability for Binary flash. It corrects
at least 2 errors per page without imposing performance penalties.
The EDC and ECC enhancements for MLC are capable of correcting up to 4 errors per page, using
two industry-standard error codes: an extended Hamming code and a BCH (Bose, Chaudhuri and
Hocquenghem) code.
The Hamming code can detect 2 errors per page and correct 1 error per page. The BCH code can
detect 4 errors per page and correct an equal number, with a safety margin that enables it to detect 5
errors per page with a probability of 99.9 percent. This combination of codes provides an even higher
rate of coverage than 2 bits per page provide for Binary flash technology.
It also ensures that the minimal amount of code required is used for detection and correction to
deliver the required reliability without degrading performance. The entire thin controller occupies
less than 5 percent of the die size for a 512Mbit device, of which only 15 percent is used for the EDC
circuit to provide exceptional detection capabilities.