M-Systems Flash Disk Pioneers Flash Memory - Manual (Page 2)

Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory
91-SR-014-02-8L 2
Introduction
Multi-Level Cell (MLC) technology greatly reduces flash die size to achieve a breakthrough cost
structure. It does this by storing 2 bits of data per physical cell instead of the traditional 1 bit per cell,
using Binary flash technology. But the increased density of the MLC flash media has grave
consequences in terms of data reliability and performance. A number of flash vendors, with varying
degrees of success, have made attempts to implement MLC technology on selected flash platforms
while overcoming its limitations.
Recently, Toshiba introduced MLC NAND technology. Although NAND constitutes a particularly
good building block for MLC technology due to its high erase and write performance and high
density (small size), MLC NAND is practically unusable for local data and code storage due to the
degradation in data reliability and performance. x2 technology, implemented in M-Systems’
DiskOnChip G3, combines advanced hardware features and customized software algorithms to boost
reliability and performance levels to rival and even exceed those of 1 bit per cell devices.
This paper discusses the MLC solutions available on the market today, their benefits and limitations,
and the hardware and software innovations of x2 technology that overcome MLC NAND limitations.
It concludes with a discussion of how the combination of MLC and x2 technologies is enabling M-
Systems’ Mobile DiskOnChip® G3 flash disk to function as the most cost-effective, fast and reliable
memory solution in mobile handsets and connected devices available on the market today.
Background
As smartphones, Personal Digital Assistants (PDAs), Set-Top Boxes (STBs) and other connected
devices offer users more and more functionality and personalization options, the storage
requirements of these devices have become substantially greater. For example, 2.5G terminals now
incorporate 128Mbit (16MByte) or even 256Mbit (32MByte) of flash memory, compared to 16 to
32Mbit (2 to 4MByte) in 2G terminals. Users will enjoy designs based on standard operating systems
with PC-like functionality and operational look-and-feel, support for multiple software applications
and more sophisticated hardware, such as color screens, and a greatly increased area to store a mix of
audio, video and text files. Despite these increasing storage requirements, the demand for sleek
packaging, particularly in the cell phone market where small size and low weight are critical design
elements, must also be met.
In an attempt to gain grounds in these highly competitive markets, vendors of flash memory are
trying to squeeze more and more capacity into constantly shrinking silicon dies, thereby optimizing
both size and cost benefits. While the obvious way to achieve this is to reduce the manufacturing
process size, few vendors have found a way to pack more information into a single memory cell. The
most mature of such technologies is Multi-Level Cell (MLC). Four levels of voltage are stored in a
single cell (thus two bits per cell), as opposed to the traditional Binary flash technology, which stores
two voltage levels (one bit per cell). The main challenges facing this technology are to program and
sense the correct voltage level accurately and quickly.
No single company has managed to live up to this challenge on its own, although a few companies
have introduced products that implement MLC technology with varying levels of success: Intel with
NOR flash, Hitachi with AND flash and most recently, Toshiba with NAND flash. MLC flash was
first mass-produced by Intel in 1999 with StrataFlash. This product succeeds in doubling the capacity