Silicon Laboratories C8051F347 - Manual (Page 120)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
120 Rev. 1.3
13.5.2. Non-multiplexed Configuration
In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a
Non-multiplexed Configuration is shown in Figure 13.3. See
Section “13.7.1. Non-multiplexed Mode” on
page 124 for more information about Non-multiplexed operation.
Figure 13.3. Non-multiplexed Configuration Example
13.6. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 13.4, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 13.2). These modes are summarized below.
More information about the different modes can be found in
Section “13.7. Timing” on page 122 .
Figure 13.4. EMIF Operating Modes
ADDRESS BUS
E
M
I
F
A[15:0]
64K X 8
SRAM
A[15:0]
DATA BUS D[7:0] I/O[7:0]
V
DD
8
WR
RD OE
WE
CE
(Optional)
EMI0CF[3:2] = 00
0xFFFF
0x0000
EMI0CF[3:2] = 11
0xFFFF
0x0000
EMI0CF[3:2] = 01
0xFFFF
0x0000
EMI0CF[3:2] = 10
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
On-Chip XRAM
0xFFFF
0x0000
Off-Chip
Memory
(Bank Select)
On-Chip XRAM
Off-Chip
Memory