Silicon Laboratories C8051F347 - Manual (Page 205)

Rev. 1.3 205
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
18. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in
Section “18.1. Enhanced Baud Rate Generation” on page 206 ). Received data buffering allows
UART0 to start reception of a second incoming data byte before software has finished reading the previous
data byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Figure 18.1. UART0 Block Diagram
UART0 Baud
Rate Generator
RI0
SCON
RI
0
TI
0
RB80 TB80 RE
N0
MC
E0
S0
M
O
DE
Tx Control
Tx Clock
Send
SBUF0
(TX Shift)
Start
Data
Write to
SBUF0
Crossbar
TX0
Shift
Zero Detector
Tx IRQ
SET
Q D
CLR
Stop Bit
TB80
SFR Bus
Serial
Port
Interrupt
TI0
Port I/O
Rx Control
Start
Rx Clock
Load
SBUF0 Shift 0x1FF RB80
Rx IRQ
Input Shift Register
(9 bits)
Load SBUF0
Read
SBUF0
SFR Bus
Crossbar
RX0
SBUF0
(RX Latch)