Capture/compare modules, Figure 22.3. pca interrupt block diagram, Section “22.2. capture/compare – Silicon Laboratories C8051F347 User Manual

Page 257

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22.2. Capture/Compare Modules

Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit
Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the
CIP-51 system controller. These registers are used to exchange data with a module and configure the
module's mode of operation.

Table 22.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA capture/com-
pare module’s operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module's
CCFn interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are rec-
ognized. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1. See
Figure 22.3 for details on the PCA interrupt configuration.

Figure 22.3. PCA Interrupt Block Diagram

Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules

PWM16 ECOM CAPP CAPN

MAT

TOG

PWM ECCF

Operation Mode

X

X

1

0

0

0

0

X

Capture triggered by positive edge on
CEXn

X

X

0

1

0

0

0

X

Capture triggered by negative edge on
CEXn

X

X

1

1

0

0

0

X

Capture triggered by transition on CEXn

X

1

0

0

1

0

0

X

Software Timer

X

1

0

0

1

1

0

X

High Speed Output

X

1

0

0

X

1

1

X

Frequency Output

0

1

0

0

X

0

1

X

8-Bit Pulse Width Modulator

1

1

0

0

X

0

1

X

16-Bit Pulse Width Modulator

X = Don’t Care

PCA0CN

C
F

C
R

C
C

F
0

C
C

F
2

C
C
F

1

C
C
F

4

C
C

F
3

PCA0MD

C

I

D

L

W
D

T
E

E
C
F

C
P
S

1

C
P
S

0

W
D

L

C
K

C
P
S

2

0

1

PCA Module 0

(CCF0)

PCA Module 1

(CCF1)

ECCF1

0

1

ECCF0

0

1

PCA Module 2

(CCF2)

ECCF2

0

1

PCA Module 3

(CCF3)

ECCF3

0

1

PCA Module 4

(CCF4)

ECCF4

PCA Counter/

Timer Overflow

0

1

Interrupt
Priority
Decoder

EPCA0

0

1

EA

0

1

PCA0CPMn

(for n = 0 to 4)

P

W

M

1
6
n

E
C

O
M

n

E
C
C
F

n

T

O
G

n

P

W

M

n

C
A
P
P

n

C
A
P
N

n

M

A
T

n

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