Watchdog timer usage, Table 22.3. watchdog timer timeout intervals1 – Silicon Laboratories C8051F347 User Manual
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Rev. 1.3
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Equation 22.4. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and
PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF4 flag (PCA0CN.4) while the WDT is
enabled.
22.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
1.
Disable the WDT by writing a ‘0’ to the WDTE bit.
2.
Select the desired PCA clock source (with the CPS2-CPS0 bits).
3.
Load PCA0CPL4 with the desired WDT update offset value.
4.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in
Idle mode).
5.
Enable the WDT by setting the WDTE bit to ‘1’.
6.
(optional) Lock the WDT (prevent WDT disable until the next system reset) by setting the
WDLCK bit to ‘1’.
7.
Write a value to PCA0CPH4 to reload the WDT.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL4 defaults to 0x00. Using Equation 22.4, this results in a WDT
timeout interval of 256 PCA clocks. Table 22.3 lists some example timeout intervals for typical system
clocks.
Table 22.3. Watchdog Timer Timeout Intervals
1
System Clock (Hz)
PCA0CPL4
Timeout Interval (ms)
12,000,000
255
65.5
12,000,000
128
33.0
12,000,000
32
8.4
24,000,000
255
32.8
24,000,000
128
16.5
24,000,000
32
4.2
1,500,000
2
255
524.3
1,500,000
2
128
264.2
1,500,000
2
32
67.6
32,768
255
24,000
32,768
128
12,093.75
32,768
32
3,093.75
Notes:
1. Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L
value of 0x00 at the update time.
2. System Clock reset frequency.
Offset
256
PCA0CPL4
256
PCA0L
–
+
=