Silicon Laboratories C8051F347 - Manual (Page 59)

Rev. 1.3 59
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
7. Comparators
C8051F34x devices include two on-chip programmable voltage Comparators. A block diagram of the com-
parators is shown in Figure 7.1, where “n” is the comparator number (0 or 1). The two Comparators oper-
ate identically with the following exceptions: (1) Their input selections differ, and (2) Comparator0 can be
used as a reset source. For input selection details, refer to SFR Definition 7.2 and SFR Definition 7.5.
Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see
Section “15.2. Port I/O Initialization” on page 147 ). Comparator0 may also be used as a
reset source (see Section “11.5. Comparator0 Reset” on page 103 ).
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 7.5). The
CMX1P1-CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the
Comparator1 negative input.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see
Section “15.3. General Purpose Port I/O” on page 150 ).