Silicon Laboratories C8051F347 - Manual (Page 61)

Rev. 1.3 61
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 7.2. Comparator Hysteresis Plot
Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown
in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is determined by
the settings of the CPnHYN bits. As shown in Figure 7.2, various levels of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see
Section “9.3. Interrupt Handler” on page 88 .) The CPnFIF flag is set
to ‘1’ upon a Comparator falling-edge, and the CPnRIF flag is set to ‘1’ upon the Comparator rising-edge.
Once set, these bits remain set until cleared by software. The output state of the Comparator can be
obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to
‘1’, and is disabled by clearing this bit to ‘0’.
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CP0+
CP0-
CP0
VIN+
VIN-
OUT
V OH
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
OUTPUT
V OL