Sony DX4 - Manual (Page 58)

AR-B1474 User¡ ¦s Guide
6-6
Parity Check
This option enables or disables parity error checking for all system RAM. This option must be Disabled if the used
DRAM SIMMs are 32-bit but not 36-bit devices.
Slow Refresh
This options sets the DRAM refresh cycle time. The settings are 15us, 30us, 60us, and 120us.
Hidden Refresh
Hidden refresh separates refreshing of AT-bus memory and local DRAM. The AT-bus controller arbitrates
between CPU accesses to the AT bus, DMA, and AT refresh, while the DRAM controller arbitrates between CPU
DRAM accesses and DRAM refresh cycle.
Ext. Cache WB/WT Feature
This option selects the type of caching algorithm of secondary cache memory. The settings are Wr-Thru or Wr-
Back.
Int. Cache WB/WT Feature
This option selects the type of caching algorithm of CPU internal cache memory. The settings are Wr-Thru or Wr-
Back.
ISA Write Cycle Insert WS
When Enabled, the wait state is added in both I/O and memory write cycle.
16-Bit ISA I/O Command WS
This option sets the wait state of 16-bit I/O cycle. The settings are 0WS, 1WS, 2WS, and 3WS.
16-Bit ISA Mem. Command WS
This option sets the wait state of 16-bit memory cycle. The settings are 0WS, 1WS, 2WS, and 3WS.
Polling Clock Select
This option sets the polling clock of IRQ and DRQ signals. The settings are CLK2, CLK2/2, CLK2/3, CLK2/4,
28.6MHz, and 14.3MHz.
6.5 POWER MANAGEMENT
This section is used to configure Power management setup for configuring power management features.
IDE Standby Mode (Min.)
This option specifies the length of time of hard disk drive inactivity that must expire before the IDE hard disk drive
is placed in IDE Standby Power Down Mode.