Silicon Laboratories SI5351A/B/C - Manual (Page 12)

S i 5 3 5 1 A / B / C
12 Preliminary Rev. 0.95
3.1.2. External Clock Input (CLKIN)
The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs.
CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to
30 MHz.
3.1.3. Voltage Control Input (VC)
The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, low-
cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 3 on page 5 for VCXO specification details.
A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 9 on page 15.
3.2. Synthesis Stages
The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply
the lower frequency input references to a high-frequency intermediate clock. The second stage uses high-
resolution MultiSynth fractional dividers to generate frequencies in the range of 1 MHz to 100 MHz. It is also
possible to generate two unique frequencies up to 160 MHz on two or more of the outputs.
A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input.
This allows each of the PLLs to lock to a different source for generating independent free-running and synchronous
clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second
stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows
any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread
spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.
Since the VCXO already generates a high-frequency intermediate clock, it is fed directly into the second stage of
synthesis. The MultiSynth high-resolution dividers synthesize the VCXO center frequency to any frequency in the
range of ~391 kHz to 160 MHz. The center frequency is then controlled (or pulled) by the VC input. An interesting
feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This creates a
VCXO with multiple output frequencies controlled from one VC input as shown in Figure 5.
Frequencies down to 8 kHz can be generated by applying the R divider at the output of the Multisynth (see
Figure 5 below).
Figure 5. Using the Si5351 as a Multi-Output VCXO
3.3. Output Stage
An additional level of division (R) is available at the output stage for generating clocks as low as 8 kHz. All output
drivers generate CMOS level outputs with separate output voltage supply pins (VDDOx) allowing a different voltage
signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks.
CLK0
VC
Multi
Synth
2
CLK1
CLK2
Additional MultiSynths
can be “linked” to the
VCXO to generate
additional clock
frequencies
XA XB
OSC
VCXO
Multi
Synth
1
Multi
Synth
0
Control
Voltage
Fixed Frequency
Crystal (non-pullable)
The clock frequency
generated from CLK0 is
controlled by the VC input
R2
R1
R0