Silicon Laboratories SI5351A/B/C - Manual (Page 38)

S i 5 3 5 1 A / B / C
38 Preliminary Rev. 0.95
Reset value = 0000 0000
Reset value = 0000 0000
Register 24. CLK3–0 Disable State
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name CLK3_DIS_STATE CLK2_DIS_STATE CLK1_DIS_STATE CLK0_DIS_STATE
Type R/W R/W R/W R/W
Bit Name Function
7:0 CLKx_DIS_STATE Clock x Disable State.
Where x = 0, 1, 2, 3. These 2 bits determine the state of the CLKx output when dis-
abled. Individual output clocks can be disabled using register Output Enable Con-
trol located at address 3. Outputs are also disabled using the OEB pin.
00: CLKx is set to a LOW state when disabled.
01: CLKx is set to a HIGH state when disabled.
10: CLKx is set to a HIGH IMPEDANCE state when disabled.
11: CLKx is NEVER DISABLED.
Register 25. CLK7–4 Disable State
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name CLK7_DIS_STATE CLK6_DIS_STATE CLK5_DIS_STATE CLK4_DIS_STATE
Type R/W R/W R/W R/W
Bit Name Function
7:0 CLKx_DIS_STATE Clock x Disable State.
Where x = 4, 5, 6, 7. These 2 bits determine the state of the CLKx output when dis-
abled. Individual output clocks can be disabled using register Output Enable Con-
trol located at address 3. Outputs are also disabled using the OEB pin.
00: CLKx is set to a LOW state when disabled.
01: CLKx is set to a HIGH state when disabled.
10: CLKx is set to a HIGH IMPEDANCE state when disabled.
11: CLKx is NEVER DISABLED.