Silicon Laboratories SI5351A/B/C - Manual (Page 34)

S i 5 3 5 1 A / B / C
34 Preliminary Rev. 0.95
Reset value = 0000 0000
Register 20. CLK4 Control
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name CLK4_PDN MS4_INT MS4_SRC CLK4_INV CLK4_SRC[1:0] CLK4_IDRV[1:0]
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7 CLK4_PDN Clock 4 Power Down.
This bit allows powering down the CLK4 output driver to conserve power when the out-
put is unused.
0: CLK4 is powered up.
1: CLK4 is powered down.
6 MS4_INT MultiSynth 4 Integer Mode.
This bit can be used to force MS4 into Integer mode to improve jitter performance.
Note that the fractional mode is necessary when a delay offset is specified for CLK4.
0: MS4 operates in fractional division mode.
1: MS4 operates in integer mode.
5 MS4_SRC MultiSynth Source Select for CLK4.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
4 CLK4_INV Output Clock 4 Invert.
0: Output Clock 4 is not inverted.
1: Output Clock 4 is inverted.
3:2 CLK4_SRC[1:0] Output Clock 4 Input Source.
These bits determine the input source for CLK4.
00: Select the XTAL as the clock source for CLK4. This option by-passes both synthe-
sis stages (PLL/VCXO & MultiSynth) and connects CLK4 directly to the oscillator
which generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK4. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK4 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK4. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
1:0 CLK4_IDRV[1:0] CLK4 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA