Silicon Laboratories SI5375 - Manual (Page 67)

Si53xx-RM
Rev. 1.2 67
6.2.1. Initiating Internal Self-Calibration
Any of the following events will trigger an automatic self-calibration:
 Internal DCO registers out-of-range, indicating the need to relock the DCO
 Setting the ICAL register bit to 1
In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm)
and is selected as the active clock at that time. The external crystal or reference clock must also be present for the
self-calibration to begin (LOSX_INT = 0 [narrowband only]).
When self-calibration is initiated the device generates an output clock if the SQ_ICAL bit is set to 0. The output
clock will appear when the device begins self-calibration. The frequency of the output clocks will change by as
much as ±20% during the ICAL process. If SQ_ICAL = 1, the output clocks are disabled during self-calibration and
will appear after the self-calibration routine is completed. The SQ_ICAL bit is self-clearing after a successful ICAL.
After a successful self-calibration has been performed with a valid input clock, it is not necessary to reinitiate a self-
calibration for subsequent losses of input clock. If the input clock is lost following self-calibration, the device enters
digital hold mode. When the input clock returns, the device relocks to the input clock without performing a self-
calibration.
After power-up and writing of dividers or PLL registers, the user must set ICAL = 1 to initiate a self-calibration. LOL
will go low when self calibration is complete. Depending on the selected value of the loop bandwidth, it may take a
few seconds more for the output frequency and phase to completely settle.
It is recommended that a software reset precede all ICALs and their associated register writes by setting
RST_REG (Register 136.7).
6.2.1.1. PLL Self-Calibration (Si5324, Si5327, Si5328, Si5369, Si5374)
Due to the low loop bandwidth of the Si5324, Si5327, Si5328, Si5369, and Si5374, the lock time of the Si5324/27/
69/75 can be longer than the lock time of the Si5326. As a method of reducing the lock time, the FAST_LOCK
register bit can be set to improve lock times. As the Si5324/27/28/69/74 data sheets indicate, FAST_LOCK is the
LSB of register 137. When FAST_LOCK is high, the lock time decreases. Because the Si5324/27/28/69/74 is
initialized with FAST_LOCK low, it must be written before ICAL. Typical Si5324/69/74 lock time (as defined from the
start of ICAL until LOL goes low) with FASTLOCK set is from one to five seconds. To reduce acquisition settling
times, it is recommended that a value of 001 be written to LOCKT (the three LSBs of register 19).
6.2.2. Input Clock Stability during Internal Self-Calibration
An ICAL must occur when the selected active CKINn clock is stable in frequency and with a frequency value that is
within the operating range that is reported by DSPLLsim. The other CKINs must be stable in frequency (< 100 ppm
from nominal) or squelched during an ICAL.
6.2.3. Self-Calibration Caused by Changes in Input Frequency
If the selected CKINn varies by 500 ppm or more in frequency since the last calibration, the device may initiate a
self-calibration.
6.2.4. Narrowband Input-to-Output Skew (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374,
Si5375, and Si5376)
The input-to-output skew is not controlled. External circuitry is required to control the input-to-output skew. Contact
Silicon Labs for further information.