Silicon Laboratories SI5375 - Manual (Page 12)

S i 5 3 x x - R M
12 Rev. 1.2
1. Any-Frequency Precision Clock Product Family Overview
Silicon Laboratories Any-Frequency Precision Clock products provide jitter attenuation and clock multiplication/
clock division for applications requiring sub 1 ps rms jitter performance. The device product family is based on
Silicon Laboratories' 3rd generation DSPLL technology, which provides any-frequency synthesis and jitter
attenuation in a highly integrated PLL solution that eliminates the need for discrete VCXO/VCSOs and loop filter
components. These devices are ideally suited for applications which require low jitter reference clocks, including
OTN (OTU-1, OTU-2, OTU-3, OTU-4), OC-48/STM-16, OC-192/STM-64, OC-768/STM-256, GbE, 10GbE, Fibre
Channel, 10GFC, synchronous Ethernet, wireless backhaul, wireless point-point infrastructure, broadcast video/
HDTV (HD SDI, 3G SDI), test and measurement, data acquisition systems, and FPGA/ASIC reference clocking.
Table 1 provides a product selector guide for the Silicon Laboratories Any-Frequency Precision Clocks. Three
product families are available. The Si5316, Si5319, Si5323, Si5324, Si5326, Si5366, and Si5368 are jitter-
attenuating clock multipliers that provide ultra-low jitter generation as low as 0.30 ps RMS. The devices vary
according to the number of clock inputs, number of clock outputs, and control method. The Si5316 is a fixed-
frequency, pin controlled jitter attenuator that can be used in clock smoothing applications. The Si5323 and Si5366
are pin-controlled jitter-attenuating clock multipliers. The frequency plan for these pin-controlled devices is
selectable from frequency lookup tables and includes common frequency translations for SONET/SDH, ITU G.709
Forward Error Correction (FEC) applications (255/238, 255/237, 255/236, 238/255, 237/255, 236/255), Gigabit
Ethernet, 10G Ethernet, 1G/2G/4G/8G/10G Fibre Channel, ATM and broadcast video (Genlock). The Si5319,
Si5324, Si5326, Si5327, Si5328, Si5368, and Si5369 are microprocessor-controlled devices that can be controlled
via an I
2
C or SPI interface. These microprocessor-controlled devices accept clock inputs ranging from 2 kHz to
710 MHz and generate multiple independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and
select frequencies to 1.4 GHz. Virtually any frequency translation combination across this operating range is
supported. Independent dividers are available for every input clock and output clock, so the Si5324, Si5326,
Si5327, Si5328, and Si5368 can accept input clocks at different frequencies and generate output clocks at different
frequencies. The Si5316, Si5319, Si5323, Si5326, Si5366, Si5368, and Si5369 support a digitally programmable
loop bandwidth that can range from 60 Hz to 8.4 kHz. An external (37–41 MHz, 55–61 MHz, and 109–125.5 MHz)
reference clock or a low-cost 114.285 MHz 3rd overtone crystal is required for these devices to enable ultra-low
jitter generation and jitter attenuation. (See "Appendix A—Narrowband References" on page 108.) The Si5324,
Si5327, and Si5369 are much lower bandwidth devices, providing a user-programmable loop bandwidth from 4 to
525 Hz. The Si5328 is an ultra-low-loop BW device that is intended for SyncE timing card applications (G.8262)
with loop BW values of from 0.05 to 6 Hz.
The Si5323, Si5324, Si5326, Si5327, Si5328, Si5366, Si5368, and Si5369 support hitless switching between input
clocks in compliance with GR-253-CORE and GR-1244-CORE that greatly minimizes the propagation of phase
transients to the clock outputs during an input clock transition (<200 ps typ). Manual, automatic revertive and
automatic non-revertive input clock switching options are available. The devices monitor the input clocks for loss-
of-signal and provide a LOS alarm when missing pulses on any of the input clocks are detected. The devices
monitor the lock status of the PLL and provide a LOL alarm when the PLL is unlocked. The lock detect algorithm
works by continuously monitoring the phase of the selected input clock in relation to the phase of the feedback
clock. The Si5324, Si5326, Si5328, Si5366, Si5368, and Si5369 monitor the frequency of the input clocks with
respect to a reference frequency applied to an input clock or the XA/XB input, and generates a frequency offset
alarm (FOS) if the threshold is exceeded. This FOS feature is available for SONET/SDH applications. Both Stratum
3/3E and SONET Minimum Clock (SMC) FOS thresholds are supported.
The Si5319, Si5323, Si5324, Si5326, Si5328, Si5366, Si5368, and Si5369 provide a digital hold capability that
allows the device to continue generation of a stable output clock when the selected input reference is lost. During
digital hold, the DSPLL generates an output frequency based on a historical average that existed a fixed amount of
time before the error event occurred, eliminating the effects of phase and frequency transients that may occur
immediately preceding entry into digital hold.
The Si5322, Si5325, Si5365, and Si5367 are frequency flexible, low jitter clock multipliers that provide jitter
generation of 0.6 ps RMS without jitter attenuation. These devices provide low jitter integer clock multiplication or
fractional clock synthesis, but they are not as frequency-flexible as the Si5319/23/24/26/66/68/69. The devices
vary according to the number of clock inputs, number of clock outputs, and control method. The Si5322 and Si5365
are pin-controlled clock multipliers. The frequency plan for these devices is selectable from frequency lookup