Silicon Laboratories SI5375 - Manual (Page 16)

S i 5 3 x x - R M
16 Rev. 1.2
3. Any-Frequency Clock Family Members
3.1. Si5316
The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC-
192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or
622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of
these clock ranges, the device can be tuned approximately 14% higher than nominal SONET/SDH frequencies, up
to a maximum of 710 MHz in the 622 MHz range. The DSPLL loop bandwidth is digitally selectable, providing jitter
performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5316 is
ideal for providing jitter attenuation in high performance timing applications. See "5. Pin Control Parts (Si5316,
Si5322, Si5323, Si5365, Si5366)" on page 37 for a complete description.
Figure 1. Si5316 Any-Frequency Jitter Attenuator Block Diagram
2
DSPLL ®
C1B
CS
LOL
BWSEL[1:0]
DBL_BY
Xtal or Refclock
SFOUT[1:0]
CKOUT+
CKOUT–
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
Control
Signal
Detect
VDD
GND
Frequency
Control
Bandwidth
Control
C2B
2
FRQSEL[1:0]
RST
0
1
RATE[1:0]
XA XB
f
OSC 2
0
1
÷ N31
÷ N32
f
3_1
f
3_2
CK1DIV
CK2DIV
f
3