Silicon Laboratories SI5375 - Manual (Page 19)

Si53xx-RM
Rev. 1.2 19
3.4. Si5323
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including
SONET OC-48/OC-192, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI). The Si5323 accepts
dual clock inputs ranging from 8 kHz to 707 MHz and generates two frequency-multiplied clock outputs ranging
from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of
popular SONET, Ethernet, Fibre Channel, and broadcast video rates. The DSPLL loop bandwidth is digitally
selectable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in high-performance timing
applications. See "5. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 37 for a complete
description.
Figure 4. Si5323 Jitter Attenuating Clock Multiplier Block Diagram
DSPLL ®
C1B
LOL
CS/CA
BWSEL[1:0]
DBL2/BY
Xtal or Refclock
SFOUT[1:0]
CKOUT_2+
CKOUT_2–
CKIN_1+
CKIN_1–
CKOUT_1+
CKOUT_1–
CKIN_2+
CKIN_2–
Control
AUTOSEL
FRQTBL
Signal
Detect
VDD
GND
Frequency
Control
Bandwidth
Control
C2B
2
2
FRQSEL[3:0]
INC
DEC
RST
0
1
RATE[1:0]
XA XB
f
OSC
2
2
0
1
0
1 f
3