SIGMA BENEFON TDP-52-SN3 - Manual (Page 42)

27.1.1999
4A0701GB.__1 8
Product: TDP-52-SN3 (Sigma Gold) / OA0701 Processor
5.1.4.7 RESET
The processor voltage regulator ERROR output resets (stops) the processor
and zeroes the controls when the battery voltage drops below 5V. When the
voltage rises again, the processor restarts.
5.1.4.8 Power Switch
The power switch (PWRKEY) is grounded, and directs the regulator I201 to
conduct when pressed. The program commences and checks the PWRSW line
to ensure that the switch is being pressed, and sets hold on the regulator for
the PWRON line. When the switch is depressed for a longer time, the program
directs power to the PWROFF line. During a short voltage break, C211 and
R211 remember the previous control, i.e. fet Q202 conducts again when the
voltage is restored within 10 seconds. The switch-fet also serves as a watch-
dog should the voltage drop or processor error-state continue; after 10
seconds, the radio will shut down completely.
Note! The RAM and ASIC circuits have their own regulator connected to the
battery to ensure an uninterrupted power supply. RAM power supply is
ensured during a battery-pack change by the battery B201.
5.1.4.9 Battery Voltage Measurement
The battery voltage is measured by an A/D converter. The converter 256 step
conversion scale is not sufficient as it stands, so the measured range is
restricted to 5...8V by the operational amplifier I303. The reference voltage for
the measurement is provided by the processor regulator 5V supply. Calibration
is done by the program against a precisely known battery voltage.
5.1.4.10 I/O ports
The ASIC I/O ports PA...PF are 8-bit hold circuits. DATA is fed to the
addressed output. When the RESET line is down (0V) all the ASIC ports are
zeroed (0V). As RESET rises again, all of the two-way I/O ports are inputs until
the program sets them to the desired state. With the radio in OFF state,
RESET is down so all of the controls are also down although ASIC is still
provided with operational voltage (VRAM).
5.1.4.11 SIS
SIS functions are provided by a mask-programmed single chip processor I503
(68HC11A8). It communicates with the host processor via ASIC with an RS232
bus (5V levels). The circuit operation is not externally visible as it is a single-
chip solution. User specific information is stored in EEPROM which CANNOT
be read from outside the chip. All external attempts to read the information
clear both EEPROM and RAM (fill with FF).