SMSC LAN9420 - Manual (Page 13)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 13 Revision 1.22 (09-25-08)
DATASHEET
1.3 PCI Bridge
LAN9420/LAN9420i implements a PCI Local Bus Specification Revision 3.0 compliant interface,
supporting the PCI Bus Power Management Interface Specification Revision 1.1.
It provides the PCI
Configuration Space Control and Status registers used to configure LAN9420/LAN9420i for PCI device
operation. Please refer to
Section 3.2, "PCI Bridge (PCIB)," on page 23 for more information.
1.4 DMA Controller
The DMA controller consists of independent Transmit and Receive engines and a control and status
register (CSR) space. The Transmit Engine transfers data from Host memory to the MAC Interface
Layer (MIL) while the Receive Engine transfers data from the MIL to Host memory. The controller
utilizes descriptors to efficiently move data from source to destination with minimal processor
intervention. Descriptors are DWORD aligned data structures in system memory that inform the DMA
controller of the location of data buffers in Host memory and also provide a mechanism for
communicating the status to the Host CPU. The DMA controller has been designed for packet-oriented
data transfer, such as frames in Ethernet. Zero copy DMA transfer is supported. Copy operations for
the purpose of data re-alignment are not required in the case where buffers are fragmented or not
aligned to a DWORD boundary. The controller can be programmed to interrupt the Host on the
occurrence of particular events, such as frame transmit or receive transfer completed, and other
normal, as well as error, conditions. Please refer to
Section 3.4, "DMA Controller (DMAC)," on page 38
for more information.
1.5 Ethernet MAC
The transmit and receive data paths are separate within the 10/100 Ethernet MAC, allowing the highest
performance, especially in full duplex mode. The data paths connect to the PCI Bridge via a DMA
engine. The MAC also implements a CSR space used by the Host to obtain status and control its
operation. The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and receive
FIFO. The MIL supports store and forward and operate on second frame mode for minimum inter-
packet gap. Please refer to
Section 3.5, "10/100 Ethernet MAC," on page 53 for more information.
1.6 Ethernet PHY
The PHY implements an IEEE 802.3 physical layer for twisted pair Ethernet applications. It can be
configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in either full
or half duplex configurations. The PHY block includes support for auto-negotiation, auto-polarity
correction and Auto-MDIX. Minimal external components are required for the utilization of the
integrated PHY. Please refer to
Section 3.6, "10/100 Ethernet PHY," on page 64 for more information.
1.7 System Control Block
The System Control Block provides the following additional elements for system operation. These
elements are controlled via its System Control and Status Registers (SCSR). Please refer to
Section
3.3, "System Control Block (SCB)," on page 28 for more information.
1.7.1 Interrupt Controller
The Interrupt Controller (INT) can be programmed to issue a PCI interrupt to the Host on the
occurrence of various events. Please refer to
Section 3.3.1, "Interrupt Controller," on page 28 for more
information.