5 phy registers, Table 4.7 phy control and status registers, Phy registers – SMSC LAN9420 User Manual
Page 135: Datasheet
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
135
Revision 1.22 (09-25-08)
DATASHEET
4.5
PHY Registers
The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC
via the MII_ACCESS and MII_DATA registers. An index is used to access individual PHY registers.
PHY Register Indexes are shown in
Table 4.7, "PHY Control and Status Registers"
below.
Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of
the PHY Basic Control Register (Reset) is set.
Table 4.7 PHY Control and Status Registers
INDEX
(IN DECIMAL)
REGISTER NAME
0
Basic Control Register
1
Basic Status Register
2
PHY Identifier 1
3
PHY Identifier 2
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Register
6
Auto-Negotiation Expansion Register
17
Mode Control/Status Register
18
Special Modes
27
Control / Status Indication Register
29
Interrupt Source Register
30
Interrupt Mask Register
31
PHY Special Control/Status Register