Table 5.11 pci i/o timing values, Datasheet – SMSC LAN9420 User Manual
Page 164
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08)
164
SMSC LAN9420/LAN9420i
DATASHEET
Note: PCI signal timing is specified with loads detailed in Section 4.2.3.2 of the PCI Local Bus
Specification, Rev. 3.0.
Note 5.15 nREQ and nGNT are point-to-point signals and have different timing characteristics than
bussed signals. All other signals are bussed.
Note 5.16 PCInRST is asserted and deasserted asynchronously with respect to the PCICLK signal.
Table 5.11 PCI I/O Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
val
PCICLK to signal valid delay - bussed signals
2
11
ns
t
val(nREQ)
PCICLK to nREQ signal valid delay (
2
12
ns
t
on
Float to active delay
2
ns
t
off
Active to float delay
28
ns
t
su
Input setup time to PCICLK - bussed signals
7
ns
t
su(nGNT)
nGNT input setup time to PCICLK (
)
10
ns
t
h
Input hold time from PCICLK
0
ns
t
rst
PCInRST active time after power stable
(
)
1
ms
t
rst-clk
PCInRST active time after PCICLK stable
(
)
100
us
t
rst-off
Rest active to output float delay (
)
40
ns