SMSC LAN9420 - Manual (Page 62)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08) 62 SMSC LAN9420/LAN9420i
DATASHEET
The RXCOE supports a maximum of two VLAN tags. If there are more than two VLAN tags, the VLAN
protocol identifier for the third tag is treated as an Ethernet type field. The checksum calculation will
begin immediately after the type field.
The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame it
calculates the 16-bit checksum. The RXCOE passes the Ethernet frame to the DMAC with the
checksum appended to the end of the frame. The RXCOE inserts the checksum immediately after the
last byte of the Ethernet frame. The frame length field (FL) of receive descriptor 0 (RDES0) indicates
that the frame size is increased by two bytes to accommodate the checksum.
Setting the RX_COE_EN bit in the Checksum Offload Engine Control Register (COE_CR) enables the
RXCOE, while the RX_COE_MODE bit selects the operating mode. When the RXCOE is disabled, the
received data is simply passed through the RXCOE unmodified.
Note: Software applications must stop the receiver and flush the RX data path before changing the
state of the RX_COE_EN or RX_COE_MODE bits.
Note: When the RXCOE is enabled, automatic pad stripping must be disabled (PADSTR bit of the
MAC Control Register (MAC_CR) ) and vice versa. These functions cannot be enabled
simultaneously.
Figure 3.23 Ethernet Frame with VLAN Tag and SNAP Header
Figure 3.24 Ethernet Frame with multiple VLAN Tags and SNAP Header
DST SRC
8
1
0
0
V
I
D
L3 Packet
F
C
S
S
N
A
P
0 S
N
A
P
1
3
L
e
n
0 1 2
{DSAP, SSAP, CTRL,
OUI[23:16]}
{OUI[15:0], PID[15:0]}
4 5 6
Calculate Checksum
DST SRC
8
1
0
0
V
I
D
L3 Packet
F
C
S
S
N
A
P
0 S
N
A
P
1
5
L
e
n
0 1 2
{DSAP, SSAP, CTRL,
OUI[23:16]}
{OUI[15:0], PID[15:0]}
6 7 8
Calculate Checksum
8
1
0
0
V
I
D
4