Figure 3.26 receive data path, 2 100base-tx receive, Nrzi and mlt3 encoding – SMSC LAN9420 User Manual

Page 67: 100m transmit driver, 100m phase lock loop (pll), 100base-tx receive, 100m receive input, Datasheet

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Datasheet

SMSC LAN9420/LAN9420i

67

Revision 1.22 (09-25-08)

DATASHEET

3.6.1.3

NRZI and MLT3 Encoding

The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a
serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a
change in the logic level represents a code bit “1” and the logic output remaining at the same level
represents a code bit “0”.

3.6.1.4

100M Transmit Driver

The MLT3 data is then passed to the analog transmitter, which launches the differential MLT-3 signal,
on outputs TPO+ and TPO-, to the twisted pair media via a 1:1 ratio isolation transformer. The
10BASE-T and 100BASE-TX signals pass through the same transformer so that common “magnetics”
can be used for both. The transmitter drives into the 100

Ω impedance of the CAT-5 cable. Cable

termination and impedance matching require external components.

3.6.1.5

100M Phase Lock Loop (PLL)

The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz
logic and the 100BASE-Tx Transmitter.

Figure 3.26 Receive Data Path

3.6.2

100BASE-TX Receive

The receive data path is shown in

Figure 3.26

. Detailed descriptions follow.

3.6.2.1

100M Receive Input

The MLT-3 from the cable is fed into the PHY (on inputs TPI+ and TPI-) via a 1:1 ratio transformer.
The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-
level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the
ADC according to the observed signal levels such that the full dynamic range of the ADC can be used.

3.6.2.2

Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,

MAC

A/D

Converter

MLT-3

Converter

NRZI

Converter

4B/5B

Decoder

Magnetics

CAT-5

RJ45

100M

PLL

Internal

MII 25MHz by 4 bits

RX_CLK

25MHz by

5 bits

NRZI

MLT-3

MLT-3

MLT-3

6 bit Data

Descrambler

and SIPO

125 Mbps Serial

DSP: Timing

recovery, Equalizer

and BLW Correction

MLT-3

MII

25MHz

by 4 bits

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