Premio Computer Premio Apollo/Shadowhawk Computer - Manual (Page 71)

CHAPTER 3 AMI
®
BIOS USER’S GUIDE
3-10
ICH Decode Select
This option allows you to select the PCI decode timing of ICH.
CPU BIST Enable
This option allows you Enable or Disable the CPU Built-In Self
Test.
ICH Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
ICH DCB Enable
This option allows you to Enable or Disable the ICH DMA
Collection Buffer for LPC I/F.
VGA Frame Buffer USWC
This option allows you to Enable or Disable the VGA frame buffer.
PCI Frame Buffer USWC
This option allows you to Enable or Disable the PCI frame buffer.