Texas Instruments DAC3482 - Manual (Page 2)

19.2MHz
TCXO
CDCE62005
DAC348X
DATA
DATA _CLK
FRAME
SYNC
PARITY
(LVDS DC Coupled)
DAC_CLK
(LVPECL AC
Coupled)
OSTR_CLK
(LVPECL AC
Coupled)
J20 RF
J19 LO
FPGA CLK
TSW3100
LVPECL DC coupled
TRF3703-15
Default TRF3703-15
Output
J7
J6
+
_
_
+
J10
Ext. CLK Output
6 V Only
J6
Power
Supply
Circuits
J21 RF
J22 LO
TRF3703-15
Default TRF3703-15
Output
J3
J2
+
_
_
+
J11
A
B
C
D
J9
Ext. CLK Input
1.5 Vrms Single Ended
1.25GHz Max
Primary Reference
(LVPECL AC coupled )
19.2 MHz Reference
LVCMOS Level
Secondary Reference for
CDCE62005 PLL Mode
Y4
Y3
Y1 Y2
PRI
SEC
J23 RF
J24 LO
TRF3703-15
Optional DAC Output
Optional TRF3703-15 Output for DAC3482 Dual DAC Mode
Introduction www.ti.com
1 Introduction
1.1 Overview
This document is intended to serve as a basic user’s guide for the DAC3484/2 EVM Revision D. The EVM
provides a basic platform to evaluate the DAC3484 and DAC3482, which are a family of 1.25GSPS, up to
16x interpolation, 16-bit high speed digital-to-analog converters. The DAC3484 is a quad-channel DAC,
and the DAC3482 is a dual-channel DAC.
The EVM includes the CDCE62005 clocking source which provides the clocks required for the DAC and
the pattern generator. The on-board TRF3703-15 modulators provide on-board IF-to-RF upconversion for
basic transmitter evaluation. This EVM is ideally suited for mating with the TSW3100 pattern generation
card for evaluating WCDMA, LTE, or other high performance modulation schemes.
1.2 EVM Block Diagram
Figure 1 shows the configuration of the EVM with the TSW3100 used for pattern generation.
Figure 1. DAC3484/DAC3482 EVM Block Diagram
2 DAC3484/DAC3482 EVM SLAU336 – March 2011
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