Texas Instruments TMS320C6455 User Manual
User ' s guide
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Table of contents
Document Outline
- TMS320C6455/C6454 DSP DDR2 Memory Controller
- Table of Contents
- Preface
- 1 Introduction
- 2 Peripheral Architecture
- 2.1 Clock Control
- 2.2 Memory Map
- 2.3 Signal Descriptions
- 2.4 Protocol Description(s)
- 2.5 Memory Width, Byte Alignment, and Endianness
- 2.6 Address Mapping
- 2.7 DDR2 Memory Controller Interface
- 2.8 Refresh Scheduling
- 2.9 Self-Refresh Mode
- 2.10 Reset Considerations
- 2.11 DDR2 SDRAM Memory Initialization
- 2.12 Interrupt Support
- 2.13 EDMA Event Support
- 2.14 Emulation Considerations
- 3 Using the DDR2 Memory Controller
- 4 DDR2 Memory Controller Registers
- 4.1 Module ID and Revision Register (MIDR)
- 4.2 DDR2 Memory Controller Status Register (DMCSTAT)
- 4.3 SDRAM Configuration Register (SDCFG)
- 4.4 SDRAM Refresh Control Register (SDRFC)
- 4.5 SDRAM Timing 1 Register (SDTIM1)
- 4.6 SDRAM Timing 2 Register (SDTIM2)
- 4.7 Burst Priority Register (BPRIO)
- 4.8 DDR2 Memory Controller Control Register (DMCCTL)
- Revision History