Texas Instruments TMS320C6455 - Manual (Page 14)

COL
MRS/EMRS
BANK
DDR2CLKOUT
DDR2CLKOUT
DCE0
DSDCKE
DSDRAS
DSDWE
DSDCAS
DBA[2:0]
DEA[13:0]
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2.4.1 Mode Register Set (MRS and EMRS)
DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for
operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-ended
strobe, etc.
The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by
issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on
DBA[1:0] selects the mode register to be written and the data on DEA[12:0] is loaded into the register.
Figure 3 shows the timing for an MRS and EMRS command.
The DDR2 memory controller only issues MRS and EMRS commands during the DDR2 memory controller
initialization sequence. For more information, see
Section 2.11 .
Figure 3. DDR2 MRS and EMRS Command
14 C6455/C6454 DDR2 Memory Controller SPRU970G – December 2005 – Revised June 2011
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