Texas Instruments TMS320C6455 - Manual (Page 31)

www.ti.com Using the DDR2 Memory Controller
3 Using the DDR2 Memory Controller
The following sections show various ways to connect the DDR2 memory controller to DDR2 memory
devices. The steps required to configure the DDR2 memory controller for external memory access are
also described.
3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM
Figure 16 , Figure 17 , and Figure 18 show a high-level view of the three memory topologies
• A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices
• A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device
• A 16-bit wide configuration interfacing to two 8-bit wide DDR2 SDRAM devices
All DDR2 SDRAM devices must be complaint to the JESD79-2B standard.
Not all of the memory topologies shown may be supported by your device. For more information, see the
device-specific data manual.
Printed circuit board (PCB) layout rules and connection requirements between the DSP and the memory
device exist and are described in a separate document. For more information, see the device-specific data
manual.
31 SPRU970G – December 2005 – Revised June 2011 C6455/C6454 DDR2 Memory Controller
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