Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
Data manual, Digital signal processor
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SM320F2812-HT
Digital Signal Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SGUS062B
June 2009
–
Revised June 2011
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Table of contents
Document Outline
- Table of Contents
- 1 Features
- 2 Introduction
- 3 Functional Overview
- 3.1 Memory Map
- 3.2 Brief Descriptions
- 3.2.1 C28x CPU
- 3.2.2 Memory Bus (Harvard Bus Architecture)
- 3.2.3 Peripheral Bus
- 3.2.4 Real-Time JTAG and Analysis
- 3.2.5 External Interface (XINTF)
- 3.2.6 Flash
- 3.2.7 L0, L1, H0 SARAMs
- 3.2.8 Boot ROM
- 3.2.9 Security
- 3.2.10 Peripheral Interrupt Expansion (PIE) Block
- 3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI)
- 3.2.12 Oscillator and PLL
- 3.2.13 Watchdog
- 3.2.14 Peripheral Clocking
- 3.2.15 Low-Power Modes
- 3.2.16 Peripheral Frames 0, 1, 2 (PFn)
- 3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
- 3.2.18 32-Bit CPU Timers (0, 1, 2)
- 3.2.19 Control Peripherals
- 3.2.20 Serial Port Peripherals
- 3.3 Register Map
- 3.4 Device Emulation Registers
- 3.5 External Interface, XINTF
- 3.6 Interrupts
- 3.7 System Control
- 3.8 OSC and PLL Block
- 3.9 PLL-Based Clock Module
- 3.10 External Reference Oscillator Clock Option
- 3.11 Watchdog Block
- 3.12 Low-Power Modes Block
- 4 Peripherals
- 4.1 32-Bit CPU-Timers 0/1/2
- 4.2 Event Manager Modules (EVA, EVB)
- 4.3 Enhanced Analog-to-Digital Converter (ADC) Module
- 4.4 Enhanced Controller Area Network (eCAN) Module
- 4.5 Multichannel Buffered Serial Port (McBSP) Module
- 4.6 Serial Communications Interface (SCI) Module
- 4.7 Serial Peripheral Interface (SPI) Module
- 4.8 GPIO MUX
- 5 Development Support
- 6 Electrical Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 Recommended Operating Conditions
- 6.3 Electrical Characteristics
- 6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
- 6.5 Current Consumption Graphs
- 6.6 Reducing Current Consumption
- 6.7 Power Sequencing Requirements
- 6.8 Signal Transition Levels
- 6.9 Timing Parameter Symbology
- 6.10 General Notes on Timing Parameters
- 6.11 Test Load Circuit
- 6.12 Device Clock Table
- 6.13 Clock Requirements and Characteristics
- 6.14 Reset Timing
- 6.15 Low-Power Mode Wakeup Timing
- 6.16 Event Manager Interface
- 6.17 General-Purpose Input/Output (GPIO) – Output Timing
- 6.18 General-Purpose Input/Output (GPIO) – Input Timing
- 6.19 SPI Master Mode Timing
- 6.20 SPI Slave Mode Timing
- 6.21 External Interface (XINTF) Timing
- 6.22 XINTF Signal Alignment to XCLKOUT
- 6.23 External Interface Read Timing
- 6.24 External Interface Write Timing
- 6.25 External Interface Ready-on-Read Timing With One External Wait State
- 6.26 External Interface Ready-on-Write Timing With One External Wait State
- 6.27 XHOLD and XHOLDA
- 6.28 XHOLD/XHOLDA Timing
- 6.29 On-Chip Analog-to-Digital Converter
- 6.29.1 ADC Absolute Maximum Ratings
- 6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions
- 6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
- 6.29.4 ADC Power-Up Control Bit Timing
- 6.29.5 Detailed Description
- 6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0)
- 6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
- 6.29.8 Definitions of Specifications and Terminology
- 6.30 Multichannel Buffered Serial Port (McBSP) Timing
- 6.31 Flash Timing
- 7 Mechanical Data
- Revision History