Rainbow Electronics MAX6900 - Manual (Page 7)

MAX6900
I
2
C-Compatible RTC in a TDFN
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An unlimited number of data bytes between the start
and stop conditions can be sent between the transmit-
ter and receiver. Each 8-bit byte is followed by an
acknowledge bit. Also, a master receiver must gener-
ate an acknowledge after each byte it receives that has
been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse (Figure 7), so
that the SDA line is stable low during the high period of
the acknowledge clock pulse (setup and hold times
must also be met). A master receiver must signal an
end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked
out of the slave. In this case, the transmitter must leave
SDA high to enable the master to generate a stop con-
dition. Any time a stop condition is received before the
current byte of data transfer is complete, the last incom-
plete byte is ignored.
The second byte of data sent after the start condition is
the Address/Command byte (Figure 8). Each data
transfer is initiated by an Address/Command byte. The
MSB (bit 7) must be a logic 1. When the MSB is zero,
Writes to the MAX6900 are disabled. Bit 6 specifies
clock/calendar data if logic 0 or RAM data if logic 1
(Tables 1 and 2). Bits 1 through 5 specify the designat-
ed registers to be input or output. The LSB (bit 0) spec-
ifies a Write operation (input) if logic 0 or Read
operation (output) if logic 1. The Command byte is
always input starting with the MSB (bit 7).
Reading from the Timekeeping
Registers
The timekeeping registers (Seconds, Minutes, Hours,
Date, Month, Day, Year, and Century) read either with a
Single Read or a Burst Read. Since the clock runs con-
tinuously and a Read takes a finite amount of time, it is
possible that the clock counters could change during a
Read operation, thereby reporting inaccurate timekeep-
ing data. In the MAX6900, the clock counter data is
buffered by a latch. Clock counter data is latched by the
I
2 C-bus-compatible read command (on the falling edge
of SCL when the Slave Acknowledge bit is sent after the
Address/Command byte has been sent by the master to
read a timekeeping register). Collision-detection circuitry
ensures that this does not happen coincident with a sec-
onds counter update to ensure accurate time data is
being read. This avoids time data changes during a
Read operation. The clock counters continue to count
and keep accurate time during the Read operation.
When using a Single Read to read each of the time-
keeping registers individually, perform error checking
D0 D6 D7
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE CLK9
CLK1 CLK2 CLK8
8 9 2 1
NOT ACKNOWLEDGE
S
Figure 7. I 2 C Bus Acknowledge
Figure 8. Address/Command Byte
/CLK
RAM
/W
A2 A1 A3 A4 A5 1
A2 A1
RD
A0 A3 A4 A5 A7 A6