Rainbow Electronics MAX5484 - Manual (Page 14)

MAX5481–MAX5484
10-Bit, Nonvolatile, Linear-Taper Digital
Potentiometers
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SPI-Compatible Serial Interface
Drive SPI/UD high to enable the 3-wire SPI-compatible
serial interface (see Figure 3). This write-only interface
contains three inputs: chip select (CS), data in
(DIN(U/D)), and data clock (SCLK(INC)). Drive CS low
to load the data at DIN(U/D) synchronously into the shift
register on each SCLK(INC) rising edge.
The WRITE command (C1, C0 = 00) requires 24 clock
cycles to transfer the command and data (Figure 4a).
The COPY commands (C1, C0 = 10 or 11) use either
eight clock cycles to transfer the command bits (Figure
4b) or 24 clock cycles with the last 16 data bits disre-
garded by the device.
After loading the data into the shift register, drive CS
high to latch the data into the appropriate control regis-
ter. Keep CS low during the entire serial data stream to
avoid corruption of the data. Table 2 shows the com-
mand decoding.
Write Wiper Register
Data written to this register (C1, C0 = 00) controls the
wiper position. The 10 data bits (D9–D0) indicate the
position of the wiper. For example, if DIN(U/D) = 00 0000
0000, the wiper moves to the position closest to L. If
DIN(U/D) = 11 1111 1111, the wiper moves closest to H.
This command writes data to the volatile random
access memory (RAM), leaving the NV register
unchanged. When the device powers up, the data
stored in the NV register transfers to the wiper register,
moving the wiper to the stored position. Figure 5 shows
how to write data to the wiper register.
CLOCK EDGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 … 24
Bit Name — — C1 C0 — — — — D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 — … —
Write Wiper Register 0 0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X … X
Copy Wiper Register
to NV Register
0 0 1 0 0 0 0 0 — — — — — — — — — — — … —
Copy NV Register to
Wiper Register
0 0 1 1 0 0 0 0 — — — — — — — — — — — … —
Table 2. Command Decoding*
*D9 is the MSB and D0 is the LSB.
X = Don’t care.
CS
t CSO
t CSS
t CL t CH
t DH t DS
t CP t CSH
t CSW
t CS1
SCLK( INC)
DIN(U/ D)
Figure 3. SPI-Compatible Serial-Interface Timing Diagram (SPI/UD = 1)