Rainbow Electronics TS81102G0 - Manual (Page 21)

21
TS81102G0
2105C–BDC–11/03
Figure 19. Synchronous Reset, 1:4 ratio, DR/2 Mode
Note: In case of low clock frequency and start with asynchronous reset, only the first data is lost and the first data to be processed is
the second one. This data is output from the DMUX through port B.
Clkn
SyncReset
Internal Port Selection
(not available out of the DEMUX)
A B C D B C A A B C D A B C D
d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11
d9 d1
d10 d2
d11 d3
d12 d4
d12 d13 d14 d15 d16
THSR
TOD
TSSR
Period of uncertainty due to desynchronization
TCPD
TDRF TDRR
I[0..9]
A[0..9]
B[0..9]
C[0..9]
D[0..9]
DR