Rainbow Electronics TS81102G0 - Manual (Page 6)

6
TS81102G0
2105C–BDC–11/03
Asynchronous
Reset
(ASYNCRESET) Figure 5. Asynchronous Reset
The Asynchronous Reset is a master reset of the port selection, which works on TTL levels. It
is active on the high level. During an asynchronous reset, the clock must be in a known state.
It is used to start the DMUX.
When it is active, it paralyzes the outputs (the output clock and output data remain at the same
level as before the asynchronous reset). When it comes back to its low level, the DMUX starts:
the outputs are active and the first processed data is on port A.
Synchronous
Reset
(SYNCRESET) Figure 6. Synchronous Reset
The DMUX can be synchronously reset to a programmable state depending on the conversion
ratio. The clock must not be stopped during reset. The synchronization signal is a clock
(SyncRest) whose frequency is FS/8*n where n is an integer (n = 1,2,3,…) in 1:8 mode and
FS/4*n in 1:4 mode. The front edge of this clock is synchronized with Clkln inside the DMUX,
and generates a 200 ps reset pulse. This reset pulse occurs during a fixed level of Clkln.
If the DMUX was synchronized with Syncreset previous to a possible loss of synchronization,
then the output data is immediately correct, no modification can be seen at the output of the
DMUX, and no data is lost (“Internal Timing Diagram” on page 3).
If the DMUX was not synchronized with SyncReset previous to a possible loss of synchroniza-
tion, then the output data and data ready of the DMUX are changed. The output data is correct
after a number of input clocks corresponding to the pipeline delay (“Timing Diagrams with Syn-
chronous Reset” on page 19).
AsyncReset
Port B selected
Port A selected
Port C selected
Port D selected
Port E selected
Port F selected
Port G selected
Port H selected
CLKIN
FS
DR/2
SyncReset = FS/8
Port B selected
Port A selected
Port C selected
Port D selected
Port E selected
Port F selected
Port G selected
Port H selected
Internal reset
pulse