Rainbow Electronics MAX5971А - Manual (Page 14)

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MAX5971A
Single-Port, 40W, IEEE 802.3af/802.3at PSE
Controller with Integrated MOSFET
During a reset, the MAX5971A latches in the state of
MIDSPAN, LEGACY, and OSC. During normal operation,
changes to these inputs are ignored.
Midspan Mode
In midspan mode, the device adopts cadence timing
during the detection phase. When cadence timing is
enabled and a failed detection occurs, the port waits
between 2s and 2.4s before attempting to detect again.
Midspan mode is activated by setting MIDSPAN high
and then powering or resetting the device. By default,
the MIDSPAN input is internally pulled high. Force
MIDSPAN low to disable this function.
Automatic Operation
The MAX5971A operates automatically after the reset
condition is cleared. The device performs detection and
classification, and powers up the port automatically once
a valid PD is detected at the port. If a valid PD is not con-
nected at the port, the MAX5971A repeats the detection
routine continuously until a valid PD is connected.
PD Detection
During normal operation, the MAX5971A probes the
output for a valid PD. A valid PD has a 25kI discov-
ery signature characteristic as specified in the IEEE
802.3af/802.3at standard. Table 1 shows the IEEE
802.3at specification for a PSE detecting a valid PD
signature.
During detection, the MAX5971A keeps the internal
MOSFET off and forces two probe voltages through DET.
The current through DET is measured as well as the volt-
age at OUT. A two-point slope measurement is used, as
specified by the IEEE 802.3af/802.3at standard, to verify
the device connected to the port.
An external diode, in series with the DET input, restricts
PD detection to the first quadrant as specified by the
IEEE 802.3af/802.3at standard. To prevent damage to
non-PD devices, and to protect itself from an output short
circuit, the MAX5971A limits the current into DET to less
than 2mA maximum during PD detection.
In midspan mode, the MAX5971A waits at least 2.0s
before attempting another detection cycle after every
failed detection. The first detection, however, happens
immediately after exiting a reset condition.
High-Capacitance Detection
The status of the LEGACY input is latched during power-
up or after reset condition is cleared. The LEGACY
input is internally pulled high enabling high-capacitance
detection. Unless high-capacitance detection is needed,
connect LEGACY to V
EE to disable this function. If high-
capacitance detection is enabled, PD signature capaci-
tances up to 47FF (typ) are accepted.
Table 1. PSE PI Detection Modes Electrical Requirements (IEEE 802.3at)
PARAMETER SYMBOL MIN MAX UNITS ADDITIONAL INFORMATION
Open-circuit voltage V OC 30 V In detection mode only
Short-circuit current I SC 5 mA In detection mode only
Valid test voltage V VALID 2.8 10 V
Voltage difference between test points
D
V
TEST
1 V
Time between any two test points t BP 2 ms
This timing implies a 500Hz
maximum probing frequency
Slew rate V SLEW 0.1 V/Fs
Accept signature resistance R GOOD 19 26.5 kI
Reject signature resistance R BAD < 15 > 33 kI
Open-circuit resistance R
OPEN
500 kI
Accept signature capacitance C GOOD 150 nF
Reject signature capacitance C BAD 10 F F
Signature offset voltage tolerance V OS 0 2.0 V
Signature offset current tolerance I OS 0 12
F
A