Rainbow Electronics ATmega64M1 - Manual (Page 242)

242
8209A–AVR–08/09
ATmega16M1/32M1/64M1
Figure 22-17. Amplifier synchronization timing diagram
ADSC is set when the amplifier output is changing due to the amplifier clock
switch
In order to have a better understanding of the functioning of the amplifier synchronization, a tim-
ing diagram example is shown
Figure 22-15 .
It is also possible to auto trigger conversion on the amplified channel. In this case, the conver-
sion is started at the next amplifier clock event following the last auto trigger event selected
thanks to the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running
mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion.
The block diagram of the two amplifiers is shown on Figure 22-18 .
Valid sample
Signal to be
measured
AMPLI_clk
(Sync Clock)
CK ADC
PSCn_ASY PSC
Block
ADSC
ADC
Activity
ADC
ADC
Sampling
ADC
Conv
ADC
Sampling
ADC
Conv
ADC
Sampling
Aborted
ADC Result
Ready
ADC Result
Ready