Rainbow Electronics ATmega64M1 - Manual (Page 306)

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8209A–AVR–08/09
ATmega16M1/32M1/64M1
28.10.1 Serial Programming Algorithm
When writing serial data to the ATmega16M1/32M1/64M1, data is clocked on the rising edge of
SCK.
When reading data from the ATmega16M1/32M1/64M1, data is clocked on the falling edge of
SCK. See
Figure 28-11 for timing details.
To program and verify the ATmega16M1/32M1/64M1 in the serial programming mode, the fol-
lowing sequence is recommended (See four byte instruction formats in
Table 28-18 ):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 8 MSB
of the address. If polling is not used, the user must wait at least t
WD_FLASH
before issuing
the next page. (See Table 28-17 .) Accessing the serial programming interface before
the Flash write operation completes can result in incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling is not used, the user must
wait at least t
WD_EEPROM
before issuing the next byte. (See Table 28-17 .) In a chip
erased device, no 0xFFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn V
CC
power off.
28.10.2 Data Polling Flash
When a page is being programmed into the Flash, reading an address location within the page
being programmed will give the value 0xFF. At the time the device is ready for a new page, the
programmed value will read correctly. This is used to determine when the next page can be writ-
ten. Note that the entire page is written simultaneously and any address within the page can be
used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming
this value, the user will have to wait for at least t
WD_FLASH
before programming the next page. As
a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to
contain 0xFF, can be skipped. See
Table 28-17 for t
WD_FLASH
value.