Rainbow Electronics ATmega128RFA1 - Manual (Page 161)

161
8266A-MCU Wireless-12/09
ATmega128RFA1
The radio transceiver has a separate reset signal. A radio transceiver reset is initiated
by setting bit TRXRST in register TRXPR. This bit is self-resetting.
The radio transceiver signal SLPTR can be controlled by the bit SLPTR in register
TRXPR and is used to set the radio transceiver into SLEEP mode (assuming
TRX_STATE is TRX_OFF). This bit has a multiple function, see section
"Low-Power 2.4
GHz Transceiver" on page 29 for a detailed description of the radio transceiver.
12.5 Supply Voltage and Leakage Control
For battery applications using deep sleep periods, the leakage current defines the
system life time. Due to the typical strong temperature dependency of the leakage
current, major contributors to the leakage budget are turned off:
• Analog and digital voltage regulator,
• Non-volatile memory (NVM),
• SRAM,
• Digital signal processor of the radio transceiver including AES engine.
If the CPU uses one of the sleep modes “power-down” or “power-save”, the above
mentioned blocks will be switched off by power switches. When the CPU wakes up, the
blocks are switched on again. There are some additional exceptions (internal voltage
regulator, SRAM, radio transceiver), see section
"Power-chain" below .
The supply voltage control is mainly hidden to the application, it is not necessary to
configure the supply voltage control. Nevertheless some configurations can be done in
order to get the maximum effect and the lowest sleep current, for details see section
"SRAM with Data Retention" on page 163 .
12.5.1 Power-chain
The following figure shows the major dependencies of the power-chain and how the
power switches are situated inside the chain.
Figure 12-1. Power-chain connections
pow er_control bandgap D V R E G
LLV R E G
drt_sw itch
S R A M # 0
drt_sw itch
S R A M #3
pow er_ sw itch
R adio
Transceiver
pow er_sw itch
N V M
pow erchain _ ok
llv reg_ok
trx 24 _sleeps
Startup and Wakeup from deep sleep
After power-on reset (POR) or wakeup from deep sleep the power switches of the
blocks will be enabled one after another (power-chained) to decrease current peaks.
The blocks will be enabled in the following order:
1. Bandgap reference and voltage regulator,
2. Digital voltage regulator (DVREG) and low leakage voltage regulator (LLVREG),
3. SRAM block #0 (lower 4k bytes),
4. SRAM block #1,
5. SRAM block #2,