2 jtag interface reads wrong data, 5 interrupt trx24_cca_ed_done may occur twice, 6 dvreg_ext bit is not write-protected – Rainbow Electronics ATmega128RFA1 User Manual
Page 514: 7 endrt bits have wrong reset value, Jtag interface reads wrong data, Interrupt trx24_cca_ed_done may occur twice, Dvreg_ext bit is not write-protected, Endrt bits have wrong reset value, Dvreg_ext
514
8266A-MCU Wireless-12/09
ATmega128RFA1
38.5.2 JTAG interface reads wrong data
If the Power Reduction Register bits associated with the SRAM’s (PRRAM3…0 in
PRR2) and the 2.4GHz Transceiver (PRTRX24 in PRR1) are set, the JTAG interface
reads wrong data. (2613).
Problem Fix/Workaround
Do not use PRRAM3…0 in PRR2 and PRTRX24 in PRR1. Force pin RSTN=0 and the
JTAG interface can erase the program memory.
38.5.3 CSMA back-off calculation has reduced degree of randomness
The CSMA back-off calculation in the transceiver extended operating modes has a
reduced degree of randomness (e.g. transceiver is in the state TX_ARET_ON) (2665).
Problem Fix/Workaround
Initialize CSMA_SEED registers with a random value.
38.5.4 Update of internal temporary registers for CSMA_SEED register may fail
The update of the internal temporary registers of the CSMA_SEED registers may fail.
Read/write operation to the CSMA_SEED registers itself works as expected (2646).
Problem Fix/Workaround
A sleep cycle of the transceiver updates the internal temporary registers.
38.5.5 Interrupt TRX24_CCA_ED_DONE may occur twice
When requesting a manually initiated CCA measurement in BUSY_RX state and during
an internal ED measurement, a TRX24_CCA_ED_DONE interrupt could be issued
immediately after the request. In this case the register bit CCA_DONE is equal to 0 and
an additional TRX24_CCA_ED_DONE interrupt is issued after finishing the CCA
measurement and register bit CCA_DONE is set to 1 (2000).
Problem Fix/Workaround
Prevent a frame reception during manually initiated CCA measurement
•
make sure that TRX_STATUS is not in RX_BUSY (i.e. start from state PLL_ON)
•
set bit RX_PDT_DIS=1
•
switch TRX_STATE to RX_ON
•
perform CCA measurement
•
set bit RX_PDT_DIS=0
38.5.6 DVREG_EXT bit is not write-protected
The external mode of the DVDD voltage regulator is not write-protected. If it is enabled
(DVREG_EXT=1 in the register VREG_CTRL) with no external power supply for DVDD,
the device leaves normal operation and can’t be recovered by the Watchdog (2658).
Problem Fix/Workaround
Do not write the bit DVREG_EXT in the register VREG_CTRL.
38.5.7 ENDRT bits have wrong reset value
The ENDRT bits in the registers DRTRAM3…0 have the wrong reset value. The data
retention of the associated SRAM in DEEP_SLEEP is disabled (2495).