Rainbow Electronics ATV750BL - Manual (Page 11)

11
ATV750B(L)
0301I–08/01
Using the
ATV750B(L)
Many Advanced
Features
The ATV750B(L) advanced flexibility packs more usable gates into 24-pins than any other
logic device. The ATV750B(L) starts with the popular 22V10 architecture, and add several
enhanced features:
• Selectable D- and T-type Registers – Each ATV750B flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are
also easily created. These options allow more efficient product term usage.
• Selectable Asynchronous Clocks – Each of the ATV750B(L) flip-flops may be clocked
by its own clock product term or directly from Pin 1 (SMD Lead 2). This removes the
constraint that all registers must use the same clock. Buried state machines, counters and
registers can all coexist in one device while running on separate clocks. Individual flip-flop
clock source selection further allows mixing higher performance pin clocking and flexible
product term clocking within one design.
• A Full Bank of Ten More Registers – The ATV750B provides two flip-flops per output
logic cell for a total of 20. Each register has its own sum term, its own reset term and its
own clock term.
• Independent I/O Pin and Feedback Paths – Each I/O pin on the ATV750B has a
dedicated input path. Each of the 20 registers has its own feedback terms into the array
as well. This feature, combined with individual product terms for each I/O’s output enable,
facilitates true bi-directional I/O design.
Programming
Software
Support
As with all other Atmel PLDs, several third-party development software products support the
ATV750B(L). Several third-party programmers support the ATV750B as well. Additionally, the
ATV750B may be programmed to perform the ATV750(L)’s functional subset (no T-type flip-
flops or pin clocking) using the ATV750(L) JEDEC file. In this case, the ATV750B becomes a
direct replacement or speed upgrade for the ATV750(L). The ATV750(L) programming algo-
rithm is different from the ATV750B algorithm. Choose the appropriate device in your
programmer menu to ensure proper programming. Please refer to the Programmable Logic
Development Tools section for a complete PLD software and programmer listing.
Synchronous
Preset and
Asynchronous
Reset
One synchronous preset line is provided for all 20 registers in the ATV750B. The appropriate
input signals to cause the internal clocks to go to a high state must be received during a syn-
chronous preset. Appropriate setup and hold times must be met, as shown in the switching
waveform diagram.
An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and
slave halves of the flip-flops are reset when the input signals received force the internal resets
high.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of the ATV750B fuse patterns. Once
the security fuse is programmed, all fuses will appear programmed during verify.
The security fuse should be programmed last, as its effect is immediate.