Rainbow Electronics ATMOS™ 1M60 - Manual (Page 13)

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5429B–IMAGE–04/05
[Preliminary] ATMOS -1M60/1M30
1. The pixel depth is set by default at 12-bit, it can be set to 10 or 8-bit. The assignment for
each configuration comply with the specifications of the CameraLink interface standard.
See register Mode Control bits [3:2] @ 204H, Internal Register Mapping page 17 .
2. In standard mode the camera provides output data on a single channel of the Camer-
aLink output interface. You might program the camera in two outputs mode, only with
the 1M60. Pixel data is de-multiplexed (odd and even pixels) on ports A, B and C of the
CameraLink interface and STROBE signal is divided by 2 (37.5 MHz).
See register mode control bit [4] @ 204H,Internal Register Mapping page 17 .
5.5 Test Pattern
In normal mode, the digital video signal from the sensor is available on the CameraLink output
interface. For test purposes a digital pattern is generated and is available instead of the video
signal in the CameraLink output interface. The pattern can be fixed or sliding. The fixed digital
pattern is ramp-up from 960 LSB code to 2271 LSB code (line width). The same pattern is
shown for each line:
Figure 5-1. Test Pattern View
The sliding pattern starts with the fixed pattern, the first code of each line is then incremented by
two on each frame. It is useful to validate the connection to the acquisition system before the
adjustment settings of the image capture. The Subsampling parameter does not affect the
pattern.
See register Mode Control bits [1:0] @ 204H, Internal Register Mapping on page 17 .
5.6 Contrast Expansion
The digital gain and offset can be adjusted via the serial communication in order to focus on a
particular part of the dynamic range.
• Gain adjusted from x1 to x32.875: code 0 to 255
• Step 0.125
• Nominal gain (factory configuration): × 1
See register Digital Gain @ 242H, Internal Register Mapping on page 17 .
• Offset adjusted from -4096 to +4095: code 0 to 8191 in 2's complement
• Step 1
• Nominal offset (factory configuration): 0
See register Digital Offset @ 244H, Internal Register Mapping on page 17 .
See register Processing Control bits [1:0] @ 202H, Internal Register Mapping on page 17 .