Rainbow Electronics ATmega8HVD - Manual (Page 19)

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8052B–AVR–09/08
ATmega4HVD/8HVD
4. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
5. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
Caution:
An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Mas-
ter Write Enable will timeout. If an interrupt routine accessing the EEPROM is interrupting
another EEPROM access, the EEARL or EEDR Register will be modified, causing the inter-
rupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft-
ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been
set, the CPU is halted for two cycles before the next instruction is executed.
Note that a BLOD reset will abort any ongoing write operation and invalidate the result.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the cor-
rect address is set up in the EEARL Register, the EERE bit must be written to a logic one to
trigger the EEPROM read. The EEPROM read access takes one instruction, and the
requested data is available immediately. When the EEPROM is read, the CPU is halted for
four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEARL Register.
The Calibrated Fast RC Oscillator is used to time the EEPROM access and the programing
time will therefore depend on the calibrated oscillator frequency.
Table 7-2 lists the typical pro-
gramming time for EEPROM access from the CPU.
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts
globally) so that no interrupts will occur during execution of these functions. The examples
also assume that no Flash Boot Loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.
Table 7-2. EEPROM Programming Time
Symbol
Number of Calibrated RC
Oscillator Cycles
Typ Programming Time,
f
OSC
= 4.0 MHz
EEPROM write
(from CPU)
13 600 3.4 ms