Rainbow Electronics ATmega8HVD - Manual (Page 72)

72
8052B–AVR–09/08
ATmega4HVD/8HVD
15.4 External Clock Source
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn
). The
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The syn-
chronized (sampled) signal is then passed through the edge detector.
Figure 15-2 shows a
functional equivalent block diagram of the Tn synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
clk
I/O
). The latch is
transparent in the high period of the internal system clock.
The edge detector generates one clk
T n
pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects. See Table 15-1 on page 73 for details.
Figure 15-2. Tn Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
ExtClk
< f
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector
uses sampling, the maximum frequency of an external clock it can detect is half the sampling
frequency (Nyquist sampling theorem). However, due to variation of the system clock fre-
quency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors)
tolerances, it is recommended that maximum frequency of an external clock source is less
than f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Note: The synchronization logic on the input pins ( Tn) is shown in Figure 15-2 .
15.5 Register Description
15.5.1 TCCRnB – Timer/Counter n Control Register B
• Bits 2, 1, 0 – CSn2, CSn1, CSn0: Clock Select0, Bit 2, 1, and 0
The Clock Select n bits 2, 1, and 0 define the prescaling source of Timer n.
Tn_sync
(To Clock
Select Logic)
Edge Detector Synchronization
D Q D Q
LE
D Q Tn
clk
I/O
Bit 7 6 5 4 3 2 1 0
- - - - - CSn2 CSn1 CSn0 TCCRnB
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0