Rainbow Electronics ATmega8HVD - Manual (Page 25)

25
8052B–AVR–09/08
ATmega4HVD/8HVD
8-1 on page 23 . The number of Ultra Low Power RC Oscillator cycles used for each time-out is
shown in Table 8-2 .
Note: 1. The actual value depends on the actual clock period of the Ultra Low Power RC Oscillator,
refer to ”Ultra Low Power RC Oscillator” on page 24 for details.
8.9 Clock Output
The CPU clock divided by 2 can be output to the PB2 pin. The CPU can enable the clock out-
put function by setting the CKOE bit in the MCU Control Register. The clock will not run in any
sleep modes.
8.10 System Clock Prescaler
The ATmega4HVD/8HVD has a System Clock Prescaler, used to prescale the Calibrated Fast
RC Oscillator. The system clock can be divided by setting the
”CLKPR – Clock Prescale Reg-
ister” on page 29 , and this enables the user to decrease or increase the system clock
frequency as the requirement for power consumption and processing power changes. This
system clock will affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O
,
clk
CPU
and clk
FLASH
are divided by a factor as shown in Table 8-4 on page 30 .
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher
than neither the clock frequency corresponding to the previous setting, nor the clock frequency
corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
may be faster than the CPU's clock frequency. It is not possible to determine the state of the
prescaler, and the exact time it takes to switch from one clock division to the other cannot be
exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and
T1 + 2*T2 before the new clock frequency is active. In this interval, two active clock edges are
produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new
prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Table 8-2. Number of Ultra Low Power RC Oscillator Cycles
Typ Time-out (1) Number of Cycles
4 ms 512
8 ms 1K
16 ms 2K
32 ms 4K
64 ms 8K
128 ms 16K
256 ms 32K
512 ms 64K