Rainbow Electronics AT25DQ321 User Manual
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AT25DQ321 [DATASHEET]
8718D–DFLASH–12/2012
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is
deasserted and the CS pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will
abort the operation and the user-programmable portion of the OTP Security Register will not be programmed. The WEL
bit in the Status Register will be reset back to the Logical 0 state if the OTP Security Register program cycle aborts due
to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being deasserted on non-byte
boundaries or because the user-programmable portion of the OTP Security Register was previously programmed.
While the device is programming the OTP Security Register, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the t
OTPP
time to determine if the data bytes have finished programming. At some point before the OTP Security Register
programming completes, the WEL bit in the Status Register will be reset back to the Logical 0 state.
If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte user
programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed again.
The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of
the buffer will be altered from its previous state when this command is issued.
Figure 10-4. Program OTP Security Register
SO
SI
SCK
CS
MSB
MSB
2
3
1
0
1
0
0
1
1
0
1
1
6
7
5
4
9
8
39
37 38
33
36
35
34
31 32
29 30
Opcode
High-impedance
A
A
A
A
A
A
MSB
D
D
D
D
D
D
D
D
Address Bits A23-A0
Data In Byte 1
MSB
D
D
D
D
D
D
D
D
Data In Byte N