5 write configuration register – Rainbow Electronics AT25DQ321 User Manual
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AT25DQ321 [DATASHEET]
8718D–DFLASH–12/2012
11.5 Write Configuration Register
The Write Configuration Register command is used to modify the QE bit of the non-volatile Configuration Register.
Before the Write Configuration Register command can be issued, the Write Enable command must have been previously
issued to set the WEL bit in the Status Register to a Logical 1.
To issue the Write Configuration Register command, the CS pin must first be asserted and the opcode of 3Eh must be
clocked into the device followed by one byte of data. The one byte of data consists of the QE bit value and seven don’t
care bits (
). Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the
QE bit of the Configuration Register will be modified within a time of t
WRCR
and the WEL bit in the Status Register will be
reset back to a Logical 0.
The complete one byte of data must be clocked into the device before the CS pin is deasserted and the CS pin must be
deasserted on byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the value of the
Configuration Register will not change and the WEL bit in the Status Register will be reset back to the Logical 0 state.
The Configuration Register is a non-volatile register and is subject to the same program/erase endurance characteristics
of the Main Memory Array.
The programming of the Configuration Register is internally self-timed and should take place in a time of t
WRCR.
While the
Configuration Register is being updated, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the t
WRCR
time to determine if
the Configuration Register has completed the programming cycle. At some point before the programming cycle
completes, the WEL bit in the Status Register will be reset back to the Logical 0 state.
Table 11-6. Write Configuration Register Format
Figure 11-5. Write Configuration Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
QE
X
X
X
X
X
X
X
SO
SI
SCK
CS
MSB
2
3
1
0
0
0
1
1
1
1
1
6
7
5
4
Opcode
10 11
9
8
14 15
13
12
0
MSB
D
X
X
X
X
X
X
X
Configuration
Register IN
High-impedance